It has been expected eagerly to reduce the electric power consumption in the power semiconductor devices which play a central role in the various uses of electric power converters such as the use for industries and the use for electric vehicles. Among the power semiconductor devices, the use of insulated-gate bipolar transistors (hereinafter referred to as “IGBTs”) has been established firmly, since the IGBTs facilitate obtaining a low ON-voltage by virtue of the conductivity modulation effects thereof and since the IGBTs are controlled easily via the gates thereof driven by a voltage. Especially, the trench-gate IGBT including a gate electrode in a trench formed in a silicon wafer surface facilitates reducing the ON-voltage, since the trench-gate IGBT facilitates increasing the density (total length) of inversion layers (channels).
In the trench-gate IGBTs, the tradeoff performance between the turnoff loss and the ON-voltage is closing to the theoretical limit by the combination of a well-known field-stop structure for stopping a depletion layer and a thinned n-type drift layer. Therefore, it is difficult to further improve the performances of the trench-gate IGBTs dramatically.
However, the power semiconductor devices, made of a compound semiconductor such as silicon carbide (SiC) and gallium nitride (GaN) and expected to be the devices of the next generation, are still on the way of development. Therefore, the mass-production of compound semiconductor IGBTs enough to replace the silicon IGBTs completely has not been realized yet. Since it is unrealistic at present to think that the silicon IGBTs vanish from the market, it is necessary to further improve the performances of the IGBTs.
As a representative IGBT of late, the IGBT, the structure of which is described in the following Patent Document 1, is well known to the persons skilled in the art. FIG. 31 is the cross sectional view of a conventional semiconductor device. In FIG. 31, the structure described in the Patent Document 1 is shown. In the IGBT shown in FIG. 31, gate trench 7 and dummy trench 8 are arranged in the device front surface such that gate trench 7 and dummy trench 8 are parallel to each other. The planar layout of gate trench 7 and dummy trench 8 is shaped with a stripe pattern. In other words, gate trench 7 and dummy trench 8 are formed in a stripe pattern in perpendicular to the plane of paper in FIG. 31.
Layers of a p-type including p-type base layer 4 are formed uniformly in the surface portion on the front surface side of the device. The p-type layer in mesa region 18 is insulated from p-type base layer 4 by gate trench 7. In other words, the p-type layer in mesa region 18 is floating p-type layer 30 having a floating potential. Floating p-type layer 30 is insulated from emitter electrode 12 by interlayer insulator film 9.
Gate trench 7 is filled with gate polysilicon 11a that works as a control electrode made of polycrystalline silicon (polysilicon). Dummy trench 8 is filled with electrically-conductive dummy polysilicon 11b with gate oxide film 10 interposed between dummy trench 8 and dummy polysilicon 11b. Dummy polysilicon 11b is connected to emitter electrode 12. In the ON-state of the gate electrode, the holes injected from p-type collector layer 3 on the back surface of the device to n-type drift layer 1 flow to emitter electrode 12 through p-type base layer 4.
By covering a large part of the front side surface of the device by floating p-type layer 30 as described above to reduce the p-type base layer 4 area in the device front surface, the holes injected into n-type drift layer 1 are accumulated in the lower part of p-type base layer 4. As a result, the ON-voltage becomes small dramatically. This effect is called an “injection enhancement (IE) effect”. By connecting electrically-conductive dummy polysilicon 11b loaded in dummy trench 8 to emitter electrode 12, it becomes possible to reduce the Miller capacitance.
As the other representative IGBT, the IGBT, the structure of which is described in the following Patent Document 2, is well known to the persons skilled in the art. FIG. 32 is the cross sectional view of the other conventional semiconductor device. In FIG. 32, the oblique view of the IGBT structure described in the Patent Document 2 is shown. In the IGBT shown in FIG. 32, gate trenches 7 are formed in the front surface of a silicon wafer including n-type drift layer 1. Between adjacent gate trenches 7, p-type base layer 4 doped more heavily than n-type drift layer 1 is formed selectively.
In the surface portion on the front surface side of p-type base layer 4, n-type emitter layer 5 and a not-shown p-type contact layer are formed selectively. In the extending direction of gate trench 7, p-type base layer 4 and n-type drift layer 1 are formed such that p-type base layer 4 and n-type drift layer 1 appear one by one in mesa region 18 and such that p-type base layers 4 are arranged scatteredly. In the direction perpendicular to the extending direction of gate trench 7, n-type drift layer 1 and p-type base layer 4 are arranged alternately with gate trench 7 interposed between n-type drift layer 1 and p-type base layer 4. In the entire active region, p-type base layers 4 are arranged in a checkered planar layout.
Since p-type base layers 4 are scattered and arranged uniformly by arranging p-type base layers 4 in a checkered planar layout, the electric field distribution in the silicon wafer becomes uniform. As a result, the breakdown voltage of the device is prevented from lowering. In gate trench 7, gate polysilicon 11a for a control electrode made of polysilicon is loaded with gate oxide film 10 interposed between gate trench 7 and gate polysilicon 11a. A not-shown interlayer insulator film is formed such that the interlayer insulator film covers the portions of the device, to which gate polysilicon 11a and the front surface of n-type drift layer 1 are exposed.
On the interlayer insulator film, a not-shown emitter electrode is formed such that the emitter electrode is in contact commonly with n-type emitter layer 5 and p-type base layer 4. Contact opening 14, through which n-type emitter layer 5 and p-type base layer 4 are in contact with the emitter electrode, is formed on n-type emitter layer 5 and p-type base layer 4. On the surface opposite to the front surface of the n-type drift layer 1 (on the back surface), n-type field-stop layer 2 and p-type collector layer 3 are formed. On the p-type collector layer 3 surface (wafer back surface), a not shown collector electrode is formed.
The conventional IGBT shown in FIG. 32 is featured by the specific configuration for avoiding the problem caused by the floating structure described later. In detail, mesa region 18 and p-type base layer 4 are made to adjoin each other so that the potential of mesa region 18 sandwiched by gate trenches 7 may not float but may follow the p-type base layer 4 potential. The specific configuration secures the gate controllability that suppresses easily, by the gate resistance, the rapid increase of the current increasing rate caused by the floating structure in the turn-on of the IGBT.
However, if the floating region is eliminated from the IGBT simply, the IGBT returns to an ordinary trench-gate one and the carrier injection enhancement effect (IE effect) is lost. As a result, the ON-voltage rises. So as not to loose the IE effects, mesa region 18 sandwiched by gate trenches 7 is divided into p-type base layers 4 and the emitter electrode is brought into contact only with divided type base layers 4. The configuration described above facilitates keeping the ON-voltage of the trench-gate IGBT at a low value and reducing the switching loss. By the configuration, the total electrical loss caused in the practical apparatuses such as an inverter is reduced. Since the region, in which the gate electrode is facing to n-type emitter layer 5, is reduced, the capacitance between the gate and emitter is reduced.
Further, by appropriately arranging the trench-gate structure, in which the spacing between the trenches is narrow to some extents, the electric field localization to the trench-gate bottom is relaxed and a high breakdown voltage is obtained. In detail, by narrowing the mesa region 18 width sandwiched by gate trenches 7, the portion of n-type drift layer 1 in mesa region 18 between gate trenches 7 is made to be depleted easily by an applied voltage of several V. By the configuration described above, the electric field distribution in the vicinity of the device front surface is made to be uniform in the OFF-state of the device and, especially, the capacitance between the gate and collector (Miller capacitance) is reduced.